Interpreting the Schematics

On first look, the schematics for the AGC are pretty hard to follow. Aside from some pullup and pulldown resistors in the restart monitor, the available Tray B modules like the oscillator and power supply, and the Tray A interface modules, they consist essentially entirely of NOR gates.

There’s a few peculiarities with the NOR gates used. Two types of NOR gates appear on the schematics. The first type is just a standard NOR gate:


The second type is almost exactly the same as the first; it’s called a “fan in gate”, and the only difference between it and the standard nor gate is that the the power pin on chips used for fan in gates is left disconnected. It is represented as a NOR gate with a black nose:


Fan in gates are used in three different ways throughout the schematics. The first, and by far the most common, is the function for which they are named: to increase the fan-in (i.e., the number of inputs) of a NOR gate. This is done simply by connecting the output of a fan in gate to the output of a regular NOR gate. Here’s a simple demonstrative example from the RUPT Service module:


Here, a six-input NOR gate is constructed using a NOR gate and a fan in gate. The principles behind this behavior are quite straightforward, given the design of the integrated circuits.


As one of the first integrated circuits ever produced, the Block II NOR gate is quite simple internally, composed of only 8 resistors and 6 bipolar junction transistors per IC (this type of circuit is known as RTL, Resistor-Transistor Logic). The above image shows the layout of one of the two NOR gates contained within each chip. Here, pin 10 connects to the power supply; pin 5 connects to ground; pins 6, 7, and 8 are the inputs of the NOR gate; and pin 9 is the output. This configuration is known as open collector: the upper (“collector”) pins of the three transistors are tied together and connected directly to the output pin of the IC. And in this, case, the resistor connecting the power pin to the rest of the circuit can be considered an internal pull-up resistor, so the external pull-up normally seen with open collector circuits isn’t (usually!) needed.

Given all of that, it’s easy to see how fan in gates work. Here’s an internal view of the above 6-input NOR example: fan_in_internals

As you can see, connecting a fan in gate to a NOR gate effectively just adds three more transistor-resistor input circuits to the NOR gate! The fan in gate’s power pin is left disconnected because otherwise the pull-up resistance would be halved. Neat, huh?

The second function performed by the fan in gates is common module outputs. It’s very closely related to the first; conceptually, it’s the same thing. The basic idea is that there’s nothing forcing a fan in gate to be close to its connected NOR gate. Indeed, there’s no particular reason why the two can’t be on different boards. This means that two completely separate modules can both drive the same signal. An example of this is the treatment of the read bus in the RUPT service module:


Here a fan in gate is being used to drive read bus line 14, with no connected NOR gate anywhere in the module. The main source of this signal is actually in four-bit module A11, here:


Note that RL14/ is facing right like an input here.

The third and final application of “fan in” gates isn’t actually for fan in expansion at all; it’s for interfacing with electrical ground support equipment (EGSE). Throughout the computer are gates like this one in the timer module:


Unlike RL14/ above, MT01 isn’t actually used anywhere in the computer proper. Therefore, instead of receiving power from any connected NOR gate, this gate would normally remain completely unpowered. Instead, this signal and those like it are routed to the “test connector” on the front of the computer. You can see that on this great image of an opened up AGC from Autopilot on Wikipedia:

Opened Apollo Guidance Computer
By Autopilot (Own work) [CC BY-SA 3.0 (], via Wikimedia Commons
The main piece of EGSE that was hooked up to the test connector was “the Monitor”. The Monitor was more or less like a JTAG debugger for the AGC. It allowed for displaying the contents central registers, stepping through instructions, setting breakpoints, displaying or modifying arbitrary memory locations, and displaying the contents of the write bus.

Anyways, the majority of the unpowered signals that run out to the test connector begin with the letter “M”, like the MT01 example above — presumably short for “Monitor”.

E-1880: A Case History of the AGC Integrated Logic Circuits shows how these signals can be used in equipment like the monitor:


The main feature here is the pull-up resistor to +V on the interface side. Note that this resistor is effectively no different than the one connected to pin 10 inside the chip — the only difference is who’s supplying the power. So these gates remain completely unpowered during flight, drawing almost no current — but as soon as you plug an EGSE device into the test port, these gates are provided power and start producing useful signals. This is an extremely useful characteristic, since power was so precious; it allowed for lots of debug circuitry to be included without incurring major power draw penalties.

Somewhat late in the program (after the flights of Apollo 11 and Apollo 12), a new special module was designed to help with diagnostics during flight. Information for debugging on orbit was limited; if any one of a number of alarms occurred, the computer would simply indicate “RESTART”, without any insight into which of the alarms had caused it. The new module, called the “Restart Monitor”, was a small module that was plugged into the test port for the duration of the flight. It allowed for computer software to read the specific alarm that had caused a restart from I/O channel 77 (more on that later). And luckily, we have the schematics for it! It just so happens that the MT01 signal shown above is one of the ones used by the Restart Monitor:


As expected from the E-1880 diagram, there’s a 3.3k pull-up resistor on the line before it’s used in any logic.

There’s one last peculiarity that’s common in the schematics. In addition to increasing the fan in of a NOR gate by attaching fan in gates, it’s also possible to increase the fan out of a gate by attaching parallel powered NOR gates. Any given NOR gate output can drive 5 connected inputs, and this number can be increased by 5 for each connected parallel gate. Here’s a fan out expansion for T02/ in the timer module:


From this, we can safely assume that T02/ is driving more than 5 inputs. But we need to be careful. There’s also no reason fan out expansion gates can’t be in other modules; and with board real estate being limited, it appears that indeed sometimes these fan out expansion gates were moved to less populated modules. Module A-24, INOUT VII, also includes some fan out gates for T02/:


So in reality T02/ is probably driving more than 15 inputs.

Armed with all of this knowledge, we can now start doing more in-depth looks at the design of each of the logic modules. But first, I’m going to give a higher level functional breakdown of larger chunks of the schematics. Stay tuned!

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