Before I start digging into the guts of the logic, I’m going to give a top-level overview of the architecture, paired with where things are in the schematics as I currently understand them. In this first part, I’ll go over timing.
Figure 3-3 from R-700 contains the basic clock architecture of the Block II AGC:
The source for all timing in the AGC was a 2.048MHz crystal oscillator, contained in aptly named Module B7 – Clock Oscillator. The output of this module, the CLOCK signal, enters into the “Pulse Forming Divider Logic”, which makes up the majority of Module A2, page 1:
This logic puts out four phases of 1.024MHz, used as the main clock for the AGC, as well as the fundamental control pulses RT (read time), CT (clear time), and WT (write time).
Page 2 of of the Timer Module contains the ring counter shown in Figure 3-3, plus start/stop logic gating the time pulse generator.
Page 3 contains a 12-step ring counter, generating the main time pules signals of the computer, T01 through T12. One iteration through the 12 time pulses is called a “Memory Cycle Time”, or MCT. During an MCT, a single Fixed or Erasable memory access could be performed. The breakdown of memory timing throughout an MCT is shown in R-393, figure 3-1:
Furthermore, instructions are defined as subsequences of control pulses that execute each time pulse. For example, here is the time pulse sequence of the TC (Transfer Control) instruction, from AGC4 Memo #9:
It triggers control pulses during time steps 1, 2, 3, 6, and 8. Unlike TC, most instructions take two or three MCTs to fully execute.
The output of the 5-step ring counter (or rather, its subsequent divide-by-2 circuit) flows into Module A1, the Scaler Module.
This is page 1, but page 2 looks pretty much identical. It generates all of the power-of-two sub-frequencies of its 102.4kHz input (51.2kHz, 25.6kHz, etc…) down to 0.390625Hz. These are used in the I/O interfaces, and during operation in standby mode. Some of them drive counters in the INOUT modules that operate as timers for the software to use.
Last in our timing discussion is Module A14, Memory Timing and Addressing.
Page 1 of the Memory Timing and Addressing module contains the “timing” portion. I’m guessing it effectively implements the timing considerations shown in R-393 figure 3-1, but I haven’t spent much time looking at this one yet.
Next up: instruction processing!