The registers in the AGC are all constructed using classic cross-coupled NOR gates. They’re divided into two classes, the “central” registers A, L, Q, and Z, and the “special” registers, which includes all of the rest of them. The central registers, as well as the banking registers, are also mapped over the lower area of Erasable memory; i.e., memory location 0 is not actually part of the Erasable memory core RAM, but rather is redirected to the A register. These registers are shown in R-700 in Table 2-II:
Outside of these, there’s a handful of non-addressable special registers:
Non-Addressable Special Registers
|B||Contains the next instruction to be executed|
|G||Memory buffer register; contains data read from or data to be written to erasable or fixed memory|
|X||One of two ALU input registers|
|Y||One of two ALU input registers|
|SQ||Upper 6 bits of current instruction; used for instruction decoding|
|S||Lower 12 bits of current instruction, used as address argument for opcode|
There’s also a couple of “fake” registers that get thrown around a lot, but don’t exist as physical flip-flops:
|C||The complement of the B register|
|U||The output of the ALU|
Before I start talking about the real schematics, I want to mention a small section from R-700 that’s particularly helpful here. It’s so good, in fact, that I’m going to just reproduce the text and accompanying figure verbatim:
An illustrative example of the NOR logic in the computer is provided by the operation of the flip-flop registers in the central processor. Digits are transferred from one register to another through a common set of lines called the write buses. The central register flip-flops are selected by read and write pulses applied to gates that either set or interrogate the flip-flop of the corresponding register. Figure 3-2 shows a hypothetical set of three flip-flops similar to those in one bit column of the computer’s central register section.
Information transfers between the registers are controlled by three clocked action pulses: read, write, and clear. Thus the WRITE BUS is normally in the 1 state, and changes to 0, while transferring a 1. Suppose REG 1 contains a 1, i.e., the top gate of its flip-flop has an output of 0. At the time that the READ 1 signal goes to 0 from its normal 1 state, the output of the read gate, CONTENT 1, becomes a 1. This propagates through a read bus fan-in and an inverter and fan-out amplifier to make WRITE BUS become 0. Suppose that WRITE 2 is made 0 concurrently with READ 1. Then the coincidence of 0’s at the write gate of REG 2 generates a 1 at the SET 2 input, thus setting the bit to 1.
If REG 1 had contained a 0, the write bus would have remained at 1, and no setting input would have appeared at the upper gate of REG 2. The CLEAR 2 pulse, that always occurs during the first half of WRITE 2, would have forced the flip-flop to the 0 state, where it would remain; whereas when a 1 is transferred, the SET 2 signal persists after the CLEAR 2, and thus forces the register back to the 1 state. Thus the simultaneous occurrence of READ 1, WRITE 2, and the short CLEAR 2 pulses transfers the content of REG 1 to REG 2. Only the content of REG 2 may be altered in the process. REG 1 and REG 3 retain their original contents. An instance of gates being used to increase fan-in is shown where several CONTENT signals are mixed together to form the signal READ BUS. An increase in fan-out is achieved by the two gates connected in parallel to form the signal WRITE BUS.
This should provide some good context for upcoming discussions. Plus, we’ve already seen the generation of the Read and Write pulses for each register in the Instructions portion of this tour (the Clear pulses are a bit weird, I’ll get to them later). As a quick refresher, many of the control pulses coming out of the Cross Point Generator modules have names like “WA” (write A register) or “RB” (read B register).
Without further ado, here’s what the real deal looks like:
This is the first page of the first of four 4 Bit Modules. All four of the 4 Bit Modules are very nearly identical, and consist of two very nearly identical pages. Furthermore, as you can kind of see above, each page is split into two almost identical “one bit columns”.
These one bit columns consist of flip-flops for the X, Y, A, L, Q, Z, B, and G registers, along with the necessary circuitry to read and write each. The X and Y registers at the top feed into one bit of the ALU, which is, quite simply, just an adder. I’ve also marked the one bit column’s “read bus” and “write bus” that correspond to R-700’s example above.
On closer inspection, though, the signals controlling these registers aren’t quite what we might be expecting based on the output of the Cross Point Generators.
Instead of WA/ (write A not), CA (clear A), and RA/ (read A not), we’ve got WAG/, CAG, and RAG/. This is because there’s one more stop for the control pulses before they reach the central registers: the Service Gates module.
This module combines the base time pulses from the Timer module with the control pulses created by the Cross Point Generators. Zooming in a bit, here’s where the WAG/ and CAG signals get created:
Also note that this is the birthplace of the register Clear signals. The Cross Point Generators don’t generate any sort of clear control pulses; instead, they’re created here as the intersection between a register Write control pulse and the CT/ timing control pulse.
At this point, the only registers we haven’t looked at are the banking registers EB and FB, and the instruction argument register S.
The banking registers are (for some reason) located in the Rupt Service Module, whose main purpose is to handle interrupts. I’ll go over the other functionalities of this module later, but for now, here’s EB and FB:
The BB register is also only “real” in the sense that it’s accessible in the AGC’s address space; only the EB and FB registers exist as physical flip-flops. BB accesses simply access both of these registers simultaneously.
Lastly, we have the S register, which is in the Parity and S Register Module. Here is the second page of that module:
It’s mostly the S register, plus a bit of logic about editing operations which I’ll talk about in the Memory part of the tour. But while we’re here, I’ll talk about what’s on the first page of this module too:
This structure computes the parity (i.e., whether the number of 1’s is even or odd) of the contents of the G register. It’s a very basic used to verify that the contents of memory are self-consistent. If for some reason a 1 unexpectedly becomes a 0 or vice-versa in memory, this circuit will catch and flag the problem before the data leaves the G register.
That’s all for now! I’ll be getting into more detailed circuit analyses before continuing this schematic overview tour. All that’s left to go, though, is Memory, Interrupts, and I/O!