Things have finally settled down in the tool hacking land and I’ve moved on to spending most of my time drawing up schematics. And all of the work I’ve been doing is now up on GitHub! Here’s links to all of the repositories, plus descriptions of what they are:
Logisim is a great tool for visualizing logic circuits, but has has two shortcomings that prevent it from being useful in its unmodified form: it doesn’t allow you to set initial conditions, and it doesn’t simulate gate propagation delay. I had addressed the former before my blog post on simulation, but propagation delays do matter in the AGC, which is why I said it had some features that prevented it from being more useful at the time.
The particular circuit that inspired to me to ahead and hack propagation delays into Logisim is this thing from page 1 of the Timer module:
My Verilog simulations showed that produces a pulse whose width is exactly 5 propagation delays on the rising edge of its input (pin B of 37148 above). Logisim disagreed:
Now that I’ve got propagation delays added in as a configurable property of logic gates, the Logisim simulation looks like this:
Unlike Logisim, my changes to KiCAD are fairly minimal; they simply flesh out the XML format for the generic netlist generator a bit. KiCAD allows you to set user-defined attributes per part. I’m using this feature to feed part parameters like initial conditions into the Verilog generator. However for multipart components, only one (seemingly random) part’s attributes actually get written to the XML file. My fork addresses this and writes out attributes for all parts of multipart components.
It’s worth noting that unlike my Logisim stuff, the official version of KiCAD will work totally fine for opening and editing the schematics and boards; my changes are only needed for proper functioning of the Verilog generator. I also might be able to get these changes pushed upstream.
This repository contains the real meat of this project: all of the KiCAD projects, schematics, board layouts, and components for the physical AGC. It’s a bit sparse at the moment, since I’ve been spending a lot of time figuring out how to group modules and how to best use KiCAD’s heirarchical sheets, but it should grow quickly.
This repository holds all of the simulation harnesses and tests for the Verilog models of the stuff in the AGC Hardware repository, plus any supporting tooling I develop. The Verilog generator that I spend so much time talking about is in here.
It also houses the autogenerated Verilog, at least for now. I’m normally not one for committing generated products to repositories, but the Verilog generation process is quite manual at the moment and I’m not aware of an easy way to script it. I’ll probably end up addressing that issue later when I’ve got multiple interfacing modules to deal with.