Let’s look at restart logic first. The five inputs on the top-left — SBY, ALGA, MSTRTP, STRT1, and STRT2 — are all possible causes for the computer to reset. Broadly speaking, these are either alarm conditions or developer-requested. I haven’t spent much time looking at the alarm logic yet, but rough definitions for them are as follows:
- SBY – Standby — set when the computer enters standby mode (this never happened during any flights)
- ALGA – Algorithm Alarm (?) — set when the running software causes a reboot-worthy exception
- MSTRTP – Monitor-requested Start — set when the Monitor (the AGC’s electrical ground support equipment, or EGSE) injects a reset
- STRT1 – Start 1 — Set if the digital Alarms module sees a voltage failure transient.
- STRT2 – Start 2 — Set by the analog alarms module, which we don’t have schematics for. It probably indicates a more serious hardware failure, but is also likely used for powerup sequencing.
Any one of these events happening sets the initial flip-flop that I’ve marked “GOJAM in progress”. “GOJAM” is the name of the AGC’s hardware restart sequence (resets JAM a GO condition into the computer). This flip-flop will remain set until the GOJ1 signal becomes set. I’ll talk about that in just a bit.
The GOJAM-in-progress register directly controls the state of the downstream register “Reset Condition Detected”, but it first goes through a pair of gates in the column I’ve marked as “Register Gating”. Register gating is a very common pattern in the AGC, and are key to the operation of its registers and write bus. The inputs to a register that are so gated are prevented from affecting that register unless other conditions are also true. Here, both T12DC/ and EVNSET/ must be low at the same time as our input in order for the set to happen.
What does this mean in practice? Well, as discussed in The Timer Module, the combination of these two signals is equivalent to the timepulse 12 signal, T12. In other words, reset conditions are prevented from reaching this register until time 12 of the MCT (memory cycle time) during which they occur. There’s a couple possible reasons why T12DC/ nor EVNSET/ is used rather than T12 directly — it reduces the load on the T12 line, and (probably more importantly) means that there’s one less gate propagation delay between the start of T12 and the latching of a reset.
Here you can see STRT1 being injected into the computer. The line I have highlighted, labeled b, represents the output of the “GOJAM in progress” register. It goes low immediately upon detection of STRT1, but the reset condition detected register, whose output is STOPA, doesn’t respond until the beginning of T12.
Once STOPA has been set, both main outputs of this logic are asserted: GOJAM and STOP. STOP is used on page 1 of the Timer module, to inhibit ODDSET/:
ODDSET/ is what makes the timepulse generator progress from T12 to T01, so as long as STOP is asserted we’re stuck in timepulse 12.
GOJAM is the main signal that prepares the computer for execution. It resets lots of conditions and registers throughout the computer, buts primary goal is to prepare the GOJ1 sequence for execution. GOJ1 is a simple unprogrammable instruction sequence that prepares the central registers for a jump to the program entry point. The ‘1’ in its name means that it’s a “stage 1” instruction — i.e., the stage 1 register needs to be set for it to run. GOJ1 is somewhat unique in that most other sequences begin during stage 0. GOJ1 starts at stage 1 because it shares the same opcode as the transfer control instruction TC. TC only has a single stage, so stage 1 of TC would otherwise be meaningless.
In order to set up GOJ1 for execution, the sequence register SQ must be cleared, the extend bit must be cleared, the stage 1 flip flop must be set, and all other stage registers must be unset.
SQ register and extend bit handling is done on page 1 of the SQ Register and Decoder module.
I’ve highlighted the path through which GOJAM clears the extend bit SQEXT and the SQ register. It’s fairly circuitous, but it resets SQEXT somewhat directly, and, during the clear time of T12, sets the CSQG (clear SQ, gated) line, which takes care of setting all of the rest of the registers in the module (SQ, the quarter-code registers, and the instruction bit 10 register) to 0.
STG1 and STG2 are respectively set and cleared directly by GOJAM. STG3 is cleared indirectly via the STRTFC signal, which is set as a result of GOJAM back in the SQ register module (it’s one of the lines that I highlighted).
The results of all of these changes lead into the instruction decoder half of the SQ Register and Decoder module.
This simple bit of logic says that if SQ is 0, we’re in stage 1, and SQEXT is not set, then the current instruction sequence is GOJ1.
Once GOJ1 has been selected as the sequence to execute, the “GOJAM in progress” register is cleared, GOJAM and STOP are deasserted, and the computer progresses out of T12 into T01 to start executing GOJ1.
As I mentioned earlier, GOJ1 is a very simple sequence. Here is its control pulse definition, taken from Hugh Blair-Smith’s AGC4 Memo #9:
Only two of the twelve timepulses generate any control pulses, and the control pulses in T02 are not actually used here. They simply don’t hurt anything, and letting GOJ1 share crosspoints with other sequences saved gates.
T08 is where the magic happens. The control pulse RSTRT puts octal 04000, the software entry point, onto the central write bus. WS and WB write this value into the S and B registers, respectively. Putting the address into the S register kicks off the core rope memory cycle to read the instruction stored there. The B register holds the next instruction to be executed, so when T12 arrives and GOJ1 has been completed, the 04000 will be loaded as the next instruction to execute.
This highlights a neat little design feature of the AGC instruction set — any literal address, when executed, jumps to itself. This happens because the opcode for TC is 000. So the whole point of GOJAM and GOJ1 is simply to set up a TC 4000 — a simple jump to the restart vector!
There’s a couple other things worth talking about in the main start/stop logic in the timer module. I’ll reproduce the image of it here:
First of note is the STRT2 input above the two registers in the middle. STRT2, being an alarm from the analog module, is apparently considered very high severity. Whereas all other alarms and reset conditions allow the current MCT to finish, STRT2 asserts GOJAM immediately, which causes the MCT to halt in its tracks and immediately start processing T12, regardless of which timepulse it was on.
The bottom half of this logic, which controls the Monitor Stop Requested logic, is never used in flight. It provides a means for the Monitor equipment to halt execution of the computer without inducing a reset, via the MSTP signal. When MSTP is asserted, the current MCT will complete up until its T12. STOP will then be asserted, preventing the computer from processing any more instructions until MSTP is deasserted.