Fourty-six years ago, man first walked on the moon. Onboard each of the two spacecraft used to get there was an innovative computer, called the Apollo Guidance Computer. It was one of the very first computers ever built using integrated circuits, and was constructed almost entirely out of NOR gates. It’s often said to be less powerful than pocket calculators; indeed, it had a 1.024MHz clock rate (executing one instruction every 12-36 ticks on average), ~4 kilobytes of RAM, and ~72 kilobytes of program memory.
There were two versions of the Apollo Guidance Computer: Block I and Block II. The Block I computer was used on the unmanned Apollo 4 and 6 flights; Block II AGCs were used on all manned missions. Architecturally, the two were quite similar. The primary differences were the integrated circuits used, the amount of memory, and the number of instructions.
A couple years ago I came across John Pultorak’s account of his successful effort to build a replica of the Block I AGC. I’ve always wanted to build a physical computer, and being a space geek this seemed like the perfect project. Pultorak’s election to build a Block I computer was based one two things: it was older (he initially wanted to build a Gemini computer), but more importantly, the best released document describing the computer’s architecture is R-393: Logical Description For The Apollo Guidance Computer (AGC4), which goes into pretty extensive detail about the Block I design.
However, since then, most of the original schematics for the Block II have become available. Since the Block II computer is what actually flew to the moon, it’s much more interesting to me. So, I’ve decided to build a Block II AGC, using these schematics along with R-393 and some other documents that have bene released. I’ll be making a special effort to stay true to the original schematics where possible. Like Pultorak, I’ll be using 74xx parts (probably 74HC series), but for the most part, it’ll be all NOR gates. This may change in the future if the number of parts gets too overwhelming, but even then it will be only logic simplification rather than any sort of radical change.
The schematics are missing most of the B modules, but that’s okay — tray B housed erasable and fixed memory, analog alarms, and oscillator. The erasable memory was Magnetic Core and the fixed memory was Core Rope. Both involve thousands of wires passing through tiny ferrite cores — something I don’t want to spent my time building (yet!). Instead, my versions of these tray B modules will house small, modern RAM and ROM chips, with the necessary circuitry to interface with the memory timing & addressing module in tray A.
Along with the schematics, the best available documents are:
- R-393: Logical Description For The Apollo Guidance Computer (AGC4) – A rather in-depth description of the Block I architecture. It has some really nice block diagrams, including a data flow diagram (with bus sizes) and a good clock chain diagram. It goes into great detail about all of the internal registers and control pulses.
- R-700: MIT’s Role in Project Apollo, Volume III: Computer Subsystem – A slightly higher-level overview focusing on the Block II computer, written around the time of Apollo 15. This details a lot of the differences between the two versions. It also goes into a lot of detail about EGSE at the end, which should be quite useful.
- AGC4 Memo #9 – Block II Instructions – Probably the best available source about the instructions available on the Block II computer. Importantly, it contains descriptions of all of the control pulses, as well as a breakdown of which control pulses are fired at each time step for each instruction.
More posts to follow detailing my current status and some initial circuit studies!